1. Field of the Invention
The present invention relates generally to a method of generating slits in power buses located on a chip. More particularly, the present invention relates to an automatic method of generating power slits in buses carrying high current.
2. Related Art
A bus is a main conductor path of electricity in a circuit. Many devices are connected to a single bus and are solely dependent on this bus for power, timing and other related dependencies. For this reason, it is critical that buses function at all times, otherwise an entire chip may fail.
In today's ever increasing search for smaller and more powerful chips, buses are increasingly required to handle larger currents (high direct current or high pulse and alternating current). Such high currents cause a number of related problems, which lead to bus failure. These problems include: stress and sub-layer gaseous release.
Stress is caused by the mechanical deformation of the bus from processing time and subsequent high temperature steps as a result of increased current at operation time. Most buses are comprised of a metal which is typically aluminum or an alloy of aluminum. Increased currents generate increased electron bombardment on atoms and lattice movement along the metal grain boundary of a bus. This in turn generates heat. The heat produces thermal expansion of the metal bus, and as a consequence, the structure of the metal bus may significantly change or eventually melt depending on the amount of current passing through the bus.
The properties of the semiconducting substrate are significantly more stable to heat due to large volume material structure able to dissipate and absorb the heat. Therefore, a semiconductor substrate will not expand or contract at the same rate as metal buses. This phenomenon causes forces to build between the semiconductor substrate (or isolation layers between metal layers, due to different thermal expansion coefficients) and the metal bus when currents pass through the bus, resulting in significant stresses and strains. Consequently, a metal bus will "buckle" or separate as a result of tensile and shear stresses caused by thermal expansion.
When metal layers are formed during manufacturing stages, gases are trapped between the metal and the semiconductor substrate. This gas can affect chemical states of devices causing undesired electrical property changes and reliability problems at a later period in time.
In order to solve the problem of stress and trapped gases, chip designers have recently begun to manually open slits in buses on a circuit chip during layout time or using other means. Openings normally occur on wider buses, because wider buses are more susceptible to stress and trapped gas problems.
FIG. 1 illustrates power buses 102 with slits 104 formed therein. The slits are referred to in this field as power slits. Power slits 104 act as a means for enabling expansion and contraction of metal power buses 102. Power slits 104 also enable gases to be released more easily from underneath power buses 102 during processing time.
Power slits 104 are opened according to current flow direction. Normally, current flow runs in a length-wise direction of a power bus 102. However, it is difficult to determine current flow 108 due to various corner cases 106 and non-orthogonal cases 110. A corner case is where two or more buses intersect. It is important not to block current flow, as shown in bus 112. This is one reason power slits 104 are manually entered in the mask database.
Nevertheless, a significant problem occurs at corner cases 106 from current flow being confined to a narrow path (also labelled as 108). As more and more current develops at a specific path 108 electro-migration occurs. Electro-migration is an undesirable result produced from too much electric current being confined to a specified area of bus 102. In this example, electro-migration is more likely to occur at a corner case 106, because electro-migration is limited to flow between power slits 104 and a boundary 114 of the aluminum power bus 102.
FIG. 2 illustrates a magnified granular view of aluminum metal at a corner case 106. FIG. 2 includes grains 202 and a bi-directional arrow path 108 indicating current flow.
Another common problem, referring back to FIG. 1, occurs with manually entering slits 104. The layout engineer examines all the buses on the chip via a computer terminal, and manually inserts all the power slits. The labor costs and time involved are currently exorbitant, not to mention error generation and verification time. With the fabrication of very large scale integrated devices, typically a chip containing one million transistors or more, requires approximately one week of time to layout power slits 104 correctly for corresponding buses 102. Furthermore, ultra large scale integrated devices typically having over ten million transistors, typically require more than one week to layout power slits 104 for corresponding buses 102.